1. Technical Field
The present invention relates generally to enablement of memory redundancy.
2. Background Art
Memory arrays in general, and static random access memories (SRAM) specifically, account for most of the silicon area on many application specific integrated circuit (ASIC) chips. These memory arrays often hurt manufacturing yields on these chips because they are such a large percentage of the chip and they tend to push the limits of a technology's manufacturing process. However, their very repetitive and predictable design lends itself well to methods of repairing the memories after the chip is manufactured. The typical approach to memory repair is to include extra, or “redundant,” rows or columns which will be “swapped” with memory elements which have defects. Conventional methods for testing and repairing fixed-design SRAM memory arrays which include row, i.e., wordline, redundancy fall into three general categories.
One technique stipulates testing all the redundant memory elements at the same time as the general memory elements (i.e., prior to fuse-blow,) and marks a chip as non-repairable if any redundant memory element fails. This technique is favored because there is a substantial cost associated with repairing a chip. Accordingly, the sooner a chip can be identified as “not fixable,” the more money can be saved in the test process because failing redundant elements will not be found at module test. However, this solution is inefficient and costly because defects found in redundant memory elements that are not needed to repair a chip will result in repairable chips being thrown away.
A second technique for testing redundant memory elements is to wait until after failing general memory elements have been replaced with redundant memory elements (i.e., after fuse-blow,) and testing the redundant memory elements as if they were the general memory elements which they are replacing. This technique is favored over the first technique because repairable chips are not thrown away when defects are found in unused redundant memory elements. However, this technique does not identify failing redundant memory elements until after fuse-blow, thus incurring the added costs of test time, fuse-blow, and possibly packaging into a module (which often comprises half the cost of a chip or more).
Finally, a third technique stipulates testing all redundant memory elements prior to replacing general memory elements, as in the first technique, but provides an additional mechanism by which failing redundant memory elements are identified and mapped around when replacing general memory elements. This technique saves test cost by reducing or eliminating the number of failing redundant memory elements after fuse-blow and identifying non-repairable chips early in the test process. However, additional costs of silicon chip area and test complexity are introduced. This extra cost is justifiable in a high-density memory array such as a dynamic RAM (DRAM,) but is not acceptable for higher-performance, lower-density memories such as SRAMs and register arrays (RAs). An additional cost is the extra test time incurred in testing the chip again at the same conditions after the memory elements have been replaced, as in the second technique.
Compilable (or customizable) memory presents further obstacles to implementing and testing redundant memory elements. For instance, testing and mapping around failed redundant memory elements is much more cumbersome in a compilable memory design.
In view of the foregoing, there is a need in the art for more efficient methods and apparatuses for testing and repairing redundant memory elements during testing.